1. Field of the Invention
The present invention relates to an operational transconductance amplifier (OTA) for amplifying an input signal with a linear transconductance and a multiplier for multiplying two input signals, and more particularly, to an OTA to be realized on metal-oxide-semiconductor (MOS) integrated circuits and a multiplier operable within wider input voltage ranges and to be realized on bipolar-MOS (Bi-MOS) integrated circuits.
2. Description of the Prior Art
FIG. 1 shows a conventional OTA of this type that has the simplest configuration, which is disclosed in Ph.D. dissertation, University of California, Berkeley, Calif., 1985, entitled "High-frequency CMOS continuous time filters" written by E. Khorramabadi. This OTA is composed of first and second source-coupled pairs of MOS field-effect transistors (MOSFET) whose drains are cross-coupled, and is termed an MOSOTA.
As shown in FIG. 1, n-channel MOS transistors M11 and M12 with the same transconductance parameter .beta..sub.1 form a first balanced differential pair that is driven by a first constant current source (current: I.sub.SS1). N-channel MOS transistors M13 and M14 with the same transconductance parameter .beta..sub.2 form a second balanced differential pair that is driven by a second constant current source (current: I.sub.SS2), where .beta..sub.1 .apprxeq..beta..sub.2.
Sources of the first and second transistors M11 and M12 are coupled together to be connected to the first current source. Sources of the third and fourth transistors M13 and M14 are coupled together to be connected to the second current source.
Gates of the transistors M11 and M13 are coupled together to be connected to one end 11 of an input end pair. Gates of the transistors M12 and M14 are coupled together to be connected to the other end 12 of the input end pair. An input voltage V.sub.i is applied across the pair of input ends 11 and 12.
Drains of the transistors M11 and M14 are coupled together and drains of the transistors M12 and M13 are coupled together. A differential output current .DELTA.I of the conventional MOSOTA is derived from the coupled drains of the transistors M11 and M14 and those of the transistors M12 and M13.
The differential output current .DELTA.I is obtained in the following manner:
Here, drain currents of the transistors M11, M12, M13 and M14 are defined as I.sub.D11, I.sub.D12, I.sub.D13, I.sub.D14, respectively; then, the differential output current .DELTA.I can be expressed as EQU .DELTA.I=(I.sub.D11 +I.sub.D14)-(I.sub.D12 +I.sub.D13).
The transconductance parameters .beta..sub.1 and .beta..sub.2 are defined as .beta..sub.1 =.mu.(C.sub.ox /2)(W1/L1) and .beta..sub.2 =.mu.(C.sub.ox /2)(W2/L2) where .mu. is the effective surface mobility of a carrier, C.sub.ox is the gate oxide capacitance per unit area, W1 and L1 are a gate-width and a gate-length of the transistors M11 and M12 and W2 and L2 are a gate-width and a gate-length of the transistors M13 and M14, respectively. Also, C.sub.ox is expressed as (.epsilon..sub.ox /t.sub.ox) where .epsilon..sub.ox and t.sub.ox are the dielectric constant and the thickness of the gate oxide, respectively.
A differential output current .DELTA.I.sub.11 (=I.sub.D11 -I.sub.D12) of the first balanced differential pair is expressed by the following equations (1a) and (1b) as ##EQU1##
Similarly, a differential output current .DELTA.I.sub.12 (=I.sub.D14 -I.sub.D13) of the second balanced differential pair is expressed by the following equations (2a) and (2b) as ##EQU2##
Here, assuming that (I.sub.SS1 /.beta..sub.1).sup.1/2 &gt;(I.sub.SS2 /.beta..sub.1).sup.1/2 since generality is not lost, the differential output current .DELTA.I of the conventional MOSOTA can be expressed by the following equation (3) as ##EQU3## where .vertline.V.sub.i .vertline..ltoreq.(I.sub.SS2 /.beta..sub.2).sup.1/2.
The equation (3) can be approximated by the following equation (4) that is obtained by using an approximation equation disclosed in ICICE Transactions on Electronics, Vol. E76-C, No. 5, pp 720, May 1993, entitled "A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter- and Source-Coupled Transistors Operable on Low Supply Voltage" written by the inventor, K. KIMURA. ##EQU4##
To make the transconductance of the MOSOTA linear in the equation (3), all of the quadratic and higher terms of the input voltage V.sub.i need to be zero. This means that the cubic term of V.sub.i, i.e., V.sub.i.sup.3 in the equation (4) needs to be zero.
Therefore, the necessary condition for making the transconductance of the conventional MOSOTA linear can be expressed by the following equation (5) as ##EQU5##
The input-output and transconductance characteristics of the conventional MOSOTA in FIG. 1, which are obtained under the above condition (5), are shown in FIGS. 2 and 3, respectively.
The transconductance characteristic curves T1 to T12 shown in FIG. 3 are obtained under the conditions in the table 1 shown below where ##EQU6##
TABLE 1 ______________________________________ CHARACTERISTIC X I.sub.SS2 .beta..sub.2 ______________________________________ T1 0.49 0 -- T2 0.242 I.sub.SS1 0.495 .beta..sub.1 T3 0.277 I.sub.SS1 0.566 .beta..sub.1 T4 0.5625 0.318 I.sub.SS1 0.566 .beta..sub.1 T5 0.375 I.sub.SS1 0.667 .beta..sub.1 T6 0.398 I.sub.SS1 0.707 .beta..sub.1 T7 0.5916 0.377 I.sub.SS1 0.637 .beta..sub.1 T8 0.7 0.410 I.sub.SS1 0.586 .beta..sub.1 T9 0.471 I.sub.SS1 0.674 .beta..sub.1 T10 0.512 I.sub.SS1 0.732 .beta..sub.1 T11 0.525 I.sub.SS1 0.751 .beta..sub.1 T12 0.81 0.680 I.sub.SS1 0.839 .beta..sub.1 ______________________________________
From the characteristics shown in FIGS. 2 and 3, it is seen that the transconductance only changes within about 4% over 70% of the operable input voltage range or more, and as a result, the linearity of the transconductance characteristic is improved in a sufficient wide input voltage range without using a complex circuit.
To realize the conventional MOSOTA on an LSI, it is required that the transconductance parameter ratio (.beta..sub.2 /.beta..sub.1) i.e., (W2/L2)/(W1/L1) has a specified value and that the driving current ratio (I.sub.SS2 /I.sub.SS1) also has a specified value. Further, to make the ratios possibly exact, the values of the transconductance parameter ratio (.beta..sub.2 /.beta..sub.1) and the driving current ratio (I.sub.SS2 /I.sub.SS1) need to be either natural numbers or ratios of natural numbers, respectively.
Therefore, unit MOS transistors has to be employed in order to realize at least one of a desired value of the transconductance parameter ratio (.beta..sub.2 /.beta..sub.1) and a desired value of the driving current ratio (I.sub.SS2 /I.sub.SS1), which increases the number of the transistors incorporated and the chip occupation area of the conventional MOSOTA.
On the other hand, FIG. 4 shows a conventional Bi-MOS multiplier, which is composed of cross-coupled, emitter-coupled pairs 50 of npn bipolar transistors Q11, Q12, Q13 and Q14 and a source-coupled pair 60 of MOS field-effect transistors M15 and M16. The cross-coupled, emitter-coupled pairs 50 are applied with a first input voltage V.sub.1 and the source-coupled pair 60 is applied with a second input voltage V.sub.2. The source-coupled pair 60 is driven by a constant current source (current: I.sub.0).
In detail, the cross-coupled, emitter-coupled pair 50 is composed of a first emitter-coupled pair of npn transistors Q11 and Q12 whose collectors are coupled together and a second emitter-coupled pair of npn transistors Q13 and Q14 whose collectors are coupled together.
The coupled collectors of the transistors Q11 and Q13 are connected to one end 56 of an output end pair. The coupled collectors of the transistors Q12 and Q14 are connected to the other end 57 of the output end pair. A differential output current .DELTA.I.sub.OUT of the conventional Bi-MOS multiplier is derived from the pair of the output ends 56 and 57.
Bases of the transistors Q11 and Q14 are coupled together to be connected to one end 51 of a first input end pair. Bases of the transistors Q12 and Q13 are coupled together to be connected to the other end 52 of the first input end pair. The first input voltage V.sub.1 is applied across the first pair of the input ends 51 and 52.
The source-coupled pair 60 is composed of n-channel MOS transistors M15 and M16 whose sources are coupled together to be connected to the constant current source.
A drain of the transistor M15 is connected to the coupled emitters of the bipolar transistors Q11 and Q12. A drain of the transistor M16 is connected to the coupled emitters of the bipolar transistors Q13 and Q14. A differential output current .DELTA.I.sub.10 is outputted from the drains of the MOS transistors M15 and M16 to drive the cross-coupled, emitter-coupled pairs 50.
A gate of the MOS transistor M15 is connected to one end 61 of a second input end pair. A base of the transistor M16 is connected to the other end 62 of the second input end pair. The second input voltage V.sub.2 is applied across the second pair of the input ends 61 and 62.
The differential output current .DELTA.I.sub.OUT of the conventional Bi-MOS multiplier is expressed by the following equations (6a) and (6b) as ##EQU7##
In the equations (6a) and (6b), .alpha..sub.Fn is the dc common-base current gain factor of an npn bipolar transistor, .beta. is the transconductance parameters of the MOS transistors M15 and M16, and V.sub.T is the thermal voltage that is expressed as V.sub.T =kT/q where k is Boltzmann's constant, T is absolute temperature in degrees Kelvin and q is the charge of an electron.
From the equations (6a) and (6b), it can be confirmed that in the cross-coupled, emitter-coupled pairs 50, the non-linearity of the differential output current .DELTA.I.sub.OUT is -7.6% when V.sub.1 =2V.sub.T so that the absolute value of the first input voltage V.sub.1 is limited to less than 2V.sub.T, i.e., .vertline.V.sub.1 .vertline.&lt;2V.sub.T.
It can also be confirmed that in the source-coupled pair 60, the input voltage range for the second input voltage V.sub.2 is decided by a ratio of the driving current I.sub.0 and the transconductance parameter .beta., i.e., (I.sub.0 /.beta.), so that the non-linearity of the differential output current .DELTA.I.sub.10 is 7% or less when the second input voltage V.sub.2 is less than 0.5.multidot.((2I.sub.0)/.beta.).sup.1/2, i.e., .vertline.V.sub.2 .vertline.&lt;0.5.multidot.[(2I.sub.0)/.beta.].sup.1/2.
As described above, with the conventional Bi-MOS multiplier in FIG. 4, as shown in the equations (6a) and (6b), the driving current I.sub.0 needs to be increased in order to widen the input voltage range for the second input voltage V.sub.2.
There are other related prior art as follows:
The Japanese Non-Examined Patent Publication No. 60-146371 (August, 1985) discloses a CMOS analog multiplier with a wide dynamic range. The CMOS analog multiplier contains a first different pair of first and second MOSFETs whose sources are coupled together and a second differential pair of third and fourth MOSFETs whose sources are coupled together.
The coupled sources of the first and second MOSFETs are connected to a first constant current sink and the coupled sources of the third and fourth MOSFETs are connected to a second constant current sink.
Gates of the first and second MOSFETs are coupled together to be connected to one end of a first input end pair. Gates of the third and fourth MOSFETs are coupled together to be connected to the other end of the first input end pair. A first input voltage to be multiplied is applied across the first input end pair.
Substrates of the first and second MOSFETs are coupled together to be connected to one end of a second input end pair. Substrates of the third and fourth MOSFETs are coupled together to be connected to the other end of the second input end pair. A second input voltage to be multiplied is applied across the second input end pair.
Drains of the first and third MOSFETs are coupled together to be connected to a first load. Drains of the second and fourth MOSFETs are coupled together to be connected to a second load. A first input voltage to be multiplied is applied across the first input end pair.
The Japanese Non-Examined Patent Publication No. 61-105912 (May, 1986) discloses a mixer circuit that can be easily formed on semiconductor integrated circuits and that can provide a sufficient conversion gain even while the input signal is small in amplitude.
The mixer circuit contains a double-balanced multiplier with two inputs and one output and a differential amplifier for amplifying two input signals and applying the input signals thus amplified to the multiplier differentially. The multiplier and the differential amplifier are composed of bipolar transistors, respectively.
The Japanese Non-Examined Patent Publication No. 3-4615 (January, 1991) discloses a multiplier in which an improved efficiency for taking out the frequency component of a clock signal can be obtained.
The multiplier contains first and second differential pairs of bipolar transistors whose respective emitters have resistors in order to widen the linear range of the input-output characteristics.
The Japanese Non-Examined Patent Publication No. 3-75977 (March, 1991) discloses a multiplier in which an output with a square-law characteristic can be obtained efficiently even if a difference between the dc biases to positive- and opposite-phase input signals.
The multiplier contains first and second differential amplifiers of bipolar transistors that are driven by the respective driving currents equal in value to each other provided at an input stage of the multiplier. First and second outputs are derived from first and second load resistances of the differential amplifiers. The first and second outputs are inputted into the multiplier through emitter followers, respectively.